⚙ OpenTools

🌳 Clock Tree / PLL Calculator

Solve PLL M/N/P/Q dividers for a target SYSCLK (and 48 MHz USB) from an input oscillator.

HSE crystal or HSI, e.g. 8 MHz.
Desired system clock after the PLL.
PLL phase detector input range.
2 MHz recommended for lowest jitter.
M divider range is 2..mMax.
N multiplier range is 50..nMax.

How it works

An STM32-style main PLL derives SYSCLK from an input oscillator through two stages:

VCOin = finput ÷ M     VCOout = VCOin × N     SYSCLK = VCOout ÷ P

Both stages have datasheet-defined valid ranges (VCO input is normally kept near 2 MHz for best jitter performance, VCO output must land inside the PLL's operating range). The tool sweeps M, derives the nearest valid N for each candidate P (∈ {2, 4, 6, 8}), and keeps only combinations that satisfy both range constraints. For each match it also searches Q (2..15) off the same VCO for the closest 48 MHz USB/SDIO clock.